sm7745d cmos series 4 pad 7 x 5mm leadless surface mount ceramic clock oscillato r cmos with enable/ disable, 3rd overtone crystal used low jitter 70.00 mhz ? 170.00 mhz standard specifications overall frequency stability sm7745d: 50 ppm, sm7744d: 25 ppm, sm7720d: 20 ppm over operating temp. range operating temperature range 0 to +70 c is standard, but can be extended to - 40 to +85 c for certain frequencies supply voltage (vcc) 5.0, 3.3, and 2.5 volts available, .01 f bypass cap recommended, consult factory for 1.8 volts symmetry (duty cycle) 40/60 to 60/40% is standard, but 45/55% at 50% of vcc is als o available (see waveform 1) output load standard load is 15 pf (typ. 1 asic) maximum, see test circu it 2 (consult factory for heavier loads) enable/disable option (e/d) see website for supply current (icc) and rise and fall times part numbering guide model frequency stability 45 = 50 ppm 44 = 25 ppm frequency in mhz special specifications (choose all that apply) y: std specs (5.0v 10% , 0 to +70 c, 40/60% symmetry) e: extended operating temperature range (- 40 to +85 c) s: 45/55% symmetry at 50% of vcc v: supply voltage of 3.3 volts 10% w: supply voltage of 2.5 volts 5% x: supply voltage of 1.8 volts 5% (consult factory) sm77 45 d v - 70.0m - 30 - xxx (internal code or blank) consult factory for available frequencies and specs. not all options available for all frequencies. a special part numbe r may be assigned. mechanical: not to scale inches (mm) sept 2004 solder pads consult factory for higher frequencies (425) 776 - 1880, fax: (425) 776 - 2760, ple - sales@pletronics.com, www.pletronics.com 8 pl tronics, inc. packaging tray or 16mm tape 8mm pitch frequency stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration a nd load output enabled when pin #1 is open or at logic ? 1 ? ; output disabled when pin #1 is at logic ? 0 ? . due to part size and factory abilities, part marking may var y from lot to lot and may contain our part number or an inte rnal code. non-std output load blank = 15 pf max, 30 = 30 pf max 1 ps rms maximum, from 12 khz to 20 mhz from carrier jitter logic levels logic ? 1 ? 90% of vcc min; logic ? 0 ? 10% of vcc max 20 = 20 ppm pl tronics , inc. 19013 36th ave. w, suite h lynnwood, wa 98036 usa manufacturer of high quality frequency control products . cmos 70 - 170 mhz, 3rd ot page 8 - 11 portions of the part number that appear after the frequency may not be marked on part (c of c provided) m .01 f bypass capacitor max 0.200 (5.08) 0.075 (1.9) 0.276 (7.0 .15) 0.197 (5.0 .15) 0.055 (1.4) 0.024 (0.60) 0.050 (1.27) 0.004 (0.10) 1 4 1 2 3 4 0.200 (5.08) 0.079 (2.0) 0.087 (2.2) 0.055 (1.4) 0.145 (3.68) 3 2 1 e/d 2 gnd 3 out 4 vcc pin signal due to part size and factory abilities, part marking may var y from lot to lot and may contain our part number or an internal code. m .01 f bypass capacitor max 0.200 (5.08) 0.075 (1.9) 0.276 (7.0 .15) 0.197 (5.0 .15) 0.055 (1.4) 0.024 (0.60) 0.050 (1.27) 0.004 (0.10) 1 4 1 2 3 4 0.200 (5.08) 0.079 (2.0) 0.087 (2.2) 0.055 (1.4) 0.145 (3.68) 3 2 1 e/d 2 gnd 3 out 4 vcc pin signal 7xywwx 106.25m ple 3esv marking examples and explanation ple = pletronics 7 = package code x = frequency stability ywwx = date code frequency in mhz 3esv = applicable specs (some internal) ple 7xyww 125.0mv
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